Course curriculum

  • 1

    Student Guide Book

    • Student Guide Book

    • Schedule/curriculum Time Table
  • 2

    Live session PDF

    • Intro_to_VLSI_Session1

    • Intro_to_VLSI_Session2

    • Intro_to_VLSI_Session3

    • Intro_to_VLSI_Session4

    • Intro_to_VLSI_Session5

    • Intro_to_VLSI_Session6

    • Intro_to_VLSI_Session7

    • Intro_to_VLSI_Session8

    • Intro_to_VLSI_Session9

    • Intro_to_VLSI_Session10

    • Intro_to_VLSI_Session11

    • Intro_to_VLSI_Session12

    • Intro_to_VLSI_Session13

    • Intro_to_VLSI_Session14

    • Intro_to_VLSI_Session15
  • 3

    Introduction

    • Uploading 1 File Introduction_to_VLSI
  • 4

    chapter 1

    • 1.Introduction
  • 5

    chapter 2

    • 2.Evolution_of_VLSI
  • 6

    chapter 3

    • 3.1.VLSI_Design_Flow

    • 3.2.VLSI_Design_Flow
  • 7

    chapter 4

    • 4. Introduction to Digital World

    • 4.1 Digital System

    • 4.2 Number Systems

    • 4.2.1 Decimal Number System

    • 4.2.2 Binary Number System

    • 4.2.3 Octal and Hexadecimal Number System

    • 4.2.4 Number System Table

    • 4.2.5 Number Base Conversions

    • 4.2.6 Exercise

    • 4.2.7 Binary Addition & Subtraction

    • 4.2.8 Complements

    • 4.2.9 Number System Further Reading

    • 4.3.1 Introduction to Logic Design

    • 4.3.2 Boolean Algebra.

    • 4.3.3 Basic Logic Gates

    • 4.3.4 XOR Gate

    • 4.3.5.1 Introduction of Error Detection & Correction

    • 4.3.5.2 Hamming Distance

    • 4.3.5.3 Parity Code

    • 4.3.5.4 Hamming Code

    • 4.3.6 NAND, NOR & XNOR Gates

    • 4.3.7 DeMorgan's Theorems

    • 4.3.8 Universal Gates

    • 4.3.9 Exercise

    • 4.4 Introduction to Combinational Circuits

    • 4.4.1 Adders

    • 4.4.2 Subtractors

    • 4.4.3 Multiplexers

    • 4.4.4 DeMultiplexers

    • 4.4.5 Decoders

    • 4.4.6 Encoders

    • 4.4.7 Comparators

    • 4.4.8 Further Reading

    • 4.5 Introduction to Sequential Circuits

    • 4.5.1 Latches

    • 4.5.2 Flip Flops

    • 4.5.3.1 Shift Registers

    • 4.5.3.2 Application of Shift Register

    • 4.5.4 Counters

    • 4.5.5 Finite State Machines

    • 4.6.1 Switch Debounce

    • 4.6.2 Timing Analysis
  • 8

    chapter 5

    • 5.1 Semiconductors Part-1

    • 5.2 Semiconductors Part-2.
  • 9

    Chapter 6

    • 6.1 FPGAs Part-1

    • 6.2 FPGAs Part-2
  • 10

    Chapter 7

    • 7.1 Basic Introduction to HDL

    • 7.2.1 Basic Concepts - Lexical Conventions

    • 7.2.2 Basic Concepts - Data Types

    • 7.2.3 Basic Concepts - System Tasks and Compiler Directives

    • 7.3 Modules and Ports

    • 7.4 Gate-Level Modeling

    • 7.5 Dataflow Modeling

    • 7.6.1 Behavioural Modeling Part-1

    • 7.6.2 Behavioural Modeling Part-2

    • 7.6.3 Behavioural Modeling Part-3

    • 7.7 Digital Circuits in Verilog Design and Conclusion
  • 11

    Zoom live session links

    • VLSI_ 1st Live Session _ 07th July 2021_ 08:00 PM

    • VLSI_ 2nd Live Session _ 13th July 2021_ 07:00 PM

    • VLSI_ 3rd Live Session _ 15th July 2021_ 07:00 PM

    • VLSI_ 4th Live Session _ 20th July 2021_ 07:00 PM

    • VLSI_ 5th Live Session _Jul 22, 2021 08:00 PM

    • VLSI_ 6th Live Session _Jul 27, 2021 07:00 PM

    • VLSI_ 7th Live Session _ Jul 29, 2021 08:00 PM

    • VLSI_ 8th Live Session _ Aug 3, 2021 08:00 PM

    • VLSI_ 9th Live Session _ Aug 5, 2021 08:00 PM

    • VLSI_ 10th Live Session _ Aug 10, 2021 08:00 PM

    • VLSI_ 11th Live Session _ Aug 12, 2021 07:00 PM

    • VLSI_ 12th Live Session _ Aug 17, 2021 07:00 PM

    • VLSI_ 13th Live Session _ Aug 19, 2021 07:00 PM

    • VLSI_14th Live Session_Aug 23, 2021 07:00 PM

    • VLSI_15th Live Session_ Aug 25, 2021 06:00 PM

    • VLSI_16th Live Session_Aug 31, 2021 07:00 PM

    • VLSI_17th Live Session_ Sep 2, 2021 07:00 PM
  • 12

    Recorded Sessions

    • VlSI_1st Session

    • VLSi_2nd Session

    • VLSI _3rd Session

    • VLSI_4th Session

    • VLSI_5th Session

    • VLSI_6th Session

    • VLSI_ Project Session_02-09-2021
  • 13

    Major Project

    • Major Project

    • Project Submission
  • 14

    Live Project Instructions

    • Orientation Meeting_Live Industrial Project
  • 15

    Internship Project-1_ UART communication to print a single character

    • Part-1

    • Part 2 - Implementation
  • 16

    Internship Project- 2_ Mealy & Moore Machines and Up Down Counter

    • Part 1 - Mealy and Moore Designs

    • Part 2 - Up Down Counter
  • 17

    Internship Project Live Sessions

    • Project-1_ UART communication to print a single character

    • Project-2_ Mealy & Moore Machines and Up Down Counter

    • Internship Project Submissions

    • Orientation meeting